The present invention relates to a phase locked loop (PLL) frequency generating circuit and to a receiver using the circuit. The present invention has particular but not exclusive application in low energy consuming devices such as battery operated wireless devices used in computer peripherals, security systems, thermostats, low power personal area network devices, telemetry systems, battery operated network interfaces such as Bluetooth and wireless Ethernet, and personal communications devices such as pagers and mobile telephones.
A problem in low power radio systems is the need to check frequently the radio channel for activity. A frequency synthesiser is often used to generate the local oscillator frequency which provides channel selection in a receiver.
A low channel spacing is achieved with a low comparison frequency in the frequency synthesiser. The low comparison frequency dictates the maximum frequency response for the loop filter. This in turn limits the settling speed of the frequency synthesiser. A significant portion of the energy needed to check the channel for activity is used waiting for the frequency synthesiser to settle. Starting the oscillator and waiting for it to settle on the correct frequency can take a longer time than the time required by the receiver to determine if there is signal present. Known techniques for reducing the lock time include switchable loop filters in which after a short period of fast settling, the loop filter characteristic is changed to give low phase noise, and fractional-N frequency synthesisers in which the comparison frequency is higher than the channel spacing and the synthesiser loop is made to settle quickly.
It is an object of the present invention to reduce the lock time in a frequency generating circuit.
According to one aspect of the present invention there is provided a phase locked loop(PLL) frequency generating circuit comprising coarse signal generating means, fine signal generating means, signal combining means having inputs coupled respectively to outputs of the coarse and fine signal generating means and an output for a predetermined frequency comprising the sum of the signals produced by the coarse and fine signal generating means.
In an embodiment of the frequency generating circuit the fine signal generating means which is low current consuming and slow to settle is energised sufficiently in advance of the coarse signal generating means which is high current consuming and fast to settle that both circuits achieve lock substantially simultaneously.
According to a second aspect of the present invention there is provided a receiver comprising an input for a radio frequency signal, a frequency down conversion stage having a first input coupled to the radio frequency input, a second input coupled to a source of local oscillator signals, and an output for a frequency down converted signal, the source of local oscillator signals comprising coarse signal generating means, fine signal generating means, and signal combining means having inputs coupled respectively to outputs of the coarse and fine signal generating means and an output for the local oscillator signal comprising a sum of the signals produced by the coarse and fine signal generating means.
US Patent Specification 3,588,732 discloses a frequency synthesiser comprising two phase locked loops(PLLs) which derive their reference frequencies from a common stable, higher frequency source which ensures that the reference frequencies, which are obtained by dividing down the common frequency, are phase locked. The divisors selected are such that the two reference frequencies differ by a relatively small quantitative frequency value, for example 100 Hz. The cited circuit differs from the frequency generating circuit made in accordance with the present invention in that the output frequencies from the two PLLs are not added to provide the output frequency. The VCO of one of the two PLLs generates the output frequency supplied to utilising equipment and also supplies this frequency to a first, non-inverting input of a signal combiner. The VCO of the second of the two PLLs is supplied to the inverting input of the signal combiner so that the difference between the two VCO frequencies is supplied to the divider of the first of the two PLLs which ensures that its VCO is able to supply small incremental value frequency steps. In this cited frequency synthesiser there is no disclosure of having independent fine and coarse PLL circuits which can be energised at different instants in time.
US Patent Specification 5,422,604 discloses a frequency synthesiser comprising first and second PLL synthesisers the outputs of which are combined. In order to reduce unwanted oscillations when changing frequency the first and second PLL synthesisers are operated so that a frequency change xcex94f is effected in a two stage operation. In the first stage the first PLL synthesiser has its frequency f1, increased by xcex94f to become (f1+xcex94f) and the second PLL synthesiser""s frequency f2 remains unchanged. In the second stage the first PLL synthesiser""s frequency is reduced by xcex94f to become f1 again and the second PLL synthesiser""s frequency is increased by xcex94f to become (f2+xcex94f). This citation does not disclose the provision of coarse and fine PLL frequency synthesisers which are energised at different times so that they achieve lock substantially simultaneously.